The semiconductor device industry has a market driven need to reduce the time required for function and speed testing of integrated circuits (ICs), in particular the high number of relatively low cost memory chips used in virtually every electronic device. Since each individual memory chip may be priced below that of the logic chips and microprocessors, and because of the large number of individual memory chips that may be used in a single electronic device, even a small reduction in overall chip cost has a large impact on the economics of both the chip manufacturer and the electronic device manufacturer. One method of reducing IC cost is to reduce the amount of time required to test each of the individual memory chips, both at wafer probe and at the finished packaged device stage at the back end of the line (BEOL).
Typically, memory chips such as dynamic random access memory (DRAM), static random access memory (SRAM), content addressable memory (CAM), and flash memory, are function tested by writing an array of binary one values (i.e., “1”), or writing an array of binary zero values (i.e., “0”), or writing alternating ones and zeros (i.e., a checkerboard), or a combination of these patterns. This is known as a single level cell, and there may also be multi-level memory cell arrays that may each store four or more different values (i.e., 0, 1, 2, 3) per cell, but the principle for testing these cells is similar.
In increase testing speed, memory chips may include “on chip” state machines (that is logic that can perform electrical operations on portions of the IC) that can write these test patterns into the memory sections of the chip as a self test and to reduce the testing time. A memory chip may have the total number of memory cells broken into groups in various ways. For example, a memory chip may have two or more banks of memory, where each bank may be broken into 2,048 blocks of memory, typically with 16 extra blocks of memory available for use as redundant memory blocks to replace defective blocks. Each block of memory may be broken down into 64 pages of memory, and each page may be formed of 1048 words, again typically with a number of redundant words to be used to replace defective words. Each word may, for example, have 32 individual bits of memory. In a function test, each of these bits must be tested to determine if the bits can be programmed to take the desired value in the allowable amount of time, at an allowable voltage level, and retain the programmed value.
In addition to simple function testing, the speed of the memory in writing and reading the data needs to be measured. For persistent memory types such as EEPROM or flash memory, the programming operation requires relatively high voltages for what is known as Fowler-Nordheim tunneling across the tunnel oxide to occur, and thus set the individual bits to either binary one or zero. After the speed of programming the memory bits is measured, the devices may be sorted into various groups, such as those that program much more rapidly than the specified rate at the normal programming voltage, those that program faster than the specified rate, and those that fail to program within the allowed time period at the normal programming voltage. It may be possible to improve the programming speed of the failed chip by increasing the programming voltage. This process may be known as trimming. All of the functional testing, the speed testing and sorting, may result in a cost of the IC chip that may reach 25% or more of the eventual IC cost. Thus, there is an industry wide problem in testing memory chips at a faster rate to reduce the cost per chip.